Dual storage node pixel for CMOS sensor

ABSTRACT

A sensor includes control circuitry and a pixel having a photo site, a first storage node and a second storage node. The control circuitry operates to transfer a first collected signal produced by light from a first image from the photo site to the first storage node during a first period, to transfer a second collected signal produced by light from a second image from the photo site to the second storage node during a second period that follows the first period and to transfer the first and second collected signals out of the pixel during a third period that follows the second period. The first storage node includes a first capacitor and a first reset gate coupled directly between the first capacitor and a reset voltage. The second storage node includes a second capacitor and a second reset gate coupled directly between the second capacitor and the reset voltage.

The priority benefit of the Jun. 5, 2001 filing date of provisionalapplication 60/295,554 is hereby claimed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a dual storage node pixel for a CMOSsensor. In particular, the invention relates to use of the two storagenodes for subtraction of background illumination.

2. Description of Related Art

In a conventional CMOS imager, a photo generated signal in a pixel isintegrated for a period of time and then subsequently read out.Generally, in some sensors, a single frame (an array of pixels) iscollected and then read out before the collection of the subsequentframe. Also, in other sensors, a single frame (an array of pixels) iscollected during an integration period that overlaps a period where thepreviously collected frame of pixels is being read out. There may besome disadvantages that arise from the time delay between collecting twoframes of data.

For example, for smart air bag deployment, at the moment of a crash, adecision must be made whether to deploy an airbag and, if so, with whatforce. This decision must be made in <10 ms with unknown and changingscene lighting. To capture an image with varying light conditions, astandard CMOS image sensor requires one exposure with a pulsed lightemitting diode (LED) source, one frame readout, a second exposurewithout the LED, a second frame readout, and finally off-chipsubtraction to form a difference image, the difference image being theilluminated image with the background illumination subtracted out. Anychange in lighting during the 1 millisecond or more interval betweenexposures creates image artifacts disrupting pattern recognition.

For example, in a 40 mile per hour crash where the occupant continues tomove at 40 miles per hour relative to a car frame mounted camera, a 1millisecond image delay represents an occupant movement of over 17millimeters. On the other hand, if the time interval between the twoimages were to be reduced to 10 microsecond, the movement would be lessthan 0.18 millimeters.

Shyh-Yih Ma and Liang-Gee Chen, describe a basic charge transfer pixelbut without most of the architectural and clocking improvementsdescribed in this improvement. See Shyh-Yih Ma and Liang-Gee Chen, ASingle-Chip CMOS APS Camera with Direct Frame Difference Output, IEEE J.Solid State Circuits, vol. 34, no. 10, pp. 1415-1418, 1999. StacyKamasz, et al., describe a dual node CCD pixel in U.S. Pat. No.5,585,652, titled Method and Apparatus for Real-Time BackgroundIllumination Subtraction.

SUMMARY OF THE INVENTION

It is an object to the present invention to overcome limitation of theprior art. This and other objects are achieved in a sensor that includescontrol circuitry and a pixel. The pixel includes a photo site, a firststorage node and a second storage node. The control circuitry causes thepixel to transfer a first collected signal from the photo site to thefirst storage node during a first period, to transfer a second collectedsignal from the photo site to the second storage node during a secondperiod that follows the first period, and to transfer the first andsecond collected signals out of the pixel during a third period thatfollows the second period.

BRIEF DESCRIPTION OF DRAWINGS

The invention will be described in detail in the following descriptionof preferred embodiments with reference to the following figureswherein:

FIG. 1 is a schematic diagram of a charge transfer embodiment of thepresent invention;

FIG. 2 is a schematic diagram of a voltage transfer embodiment of thepresent invention;

FIGS. 3-6 are schematic diagrams of alternative embodiments of thepresent invention involving reset circuitry and single and dual outputbuffer circuitry;

FIGS. 7-11 are schematic diagrams of alternative embodiments of a pixelaccording to the present invention; and

FIG. 12 is a block diagram of a sensor according to the presentinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

It is advantageous, in many applications, to collect and store two ormore frames worth of data and then subsequently read these frames out ata subsequent point in time. One example of such an application is theimaging of a scene illuminated by a strobed light source (e.g. laserdiode) that is relatively weak in comparison to a strong backgroundillumination (e.g. sunlight in an outdoor scene). With a dual node pixelone scene is collected and stored during a period of duration T duringwhich the strobed source is turned on so that the collected lightincludes the scene illumination provided by the strobed source plus thestrong background source. The signal is then stored on storage site #1.The second scene is subsequently collected during another period ofduration T during which the strobed source is turned off so that thecollected light includes only the scene illumination provided by thestrong background. The signal is then stored on storage site #2.Subsequently, the two sites are read out and subtracted from each otherproducing a difference signal that corresponds to the scene asilluminated only by the strobed source.

A dual node pixel of the present invention is applied in order tocompensate for performance limitations in a conventional pixel. Forexample, a conventional CMOS pixel for synchronous imaging contains adistinct photosite and storage/sense node—during the integration periodcharge is collected in the photosite of each pixel for a small fractionof the frame time and then the signal in each photosite is transferredto the corresponding storage/sense node for subsequent read out. Howeverduring the read out period there can be significant crosstalk from thephotosite into the storage node (i.e., a small fraction of the signalgenerated by light falling on the photosite, all of which ideally is tobe ignored, ends up producing charge in the storage nodes)“contaminating” the snap shot image stored on those sites. For veryshort exposures only a small amount of signal charge iscollected—however during the much longer readout a considerable amountof crosstalk signal can accumulate, even if only a small percentage ofthe light falling on the sensor during the read out ends up in thestorage sites. With a dual node pixel, the signal collected during theintegration period is stored on one of the storage sites while nothingis explicitly stored on the second storage site. However during the longread out phase both storage sites should collect equal amounts of signaldue to crosstalk. If both sites are read out and differenced then allthat should be left is the desired signal from the short exposure time.

In yet another application, motion is detected and measured bydifferencing two closely spaced exposures. One can generate an outputsignal that is non-zero only for the parts of the scene that changedbetween the two exposures.

Two different embodiments for a dual node pixel are describedrepresenting a charge transfer architecture and a voltage transferarchitecture. The first requires that the signal charge be transferredfrom the photosite to two storage capacitors as illustrated in FIG. 1.The charge is transferred across two distinct transfer gates. Thestorage capacitors also function as sense nodes allowing the signal tobe transferred from the charge domain to the voltage domain for readout.On readout, the voltage on storage capacitor #1 is first buffered andput onto the column data bus to be read off-array. Then, the capacitoris reset and read once more to affect correlated double sampling. Offarray the two levels are differenced to produce a signal level forcapacitor #1 that has the FPN (fixed pattern noise) from the readoutchain eliminated. The same series of operations is applied to capacitor#2. Then off-array the two signals from the two capacitors aresubtracted. A similar but more basic architecture was described by Maand Chen in 1999, though we are suggesting several improvements to thearchitecture that they presented.

If there is only a single common output buffer for the pixel, then thesecond read of each storage node after they have been reset to removeoffsets (e.g., for the purpose of correlated double or differencesampling), is not strictly necessary. This is because the signals fromeach of the two storage nodes will be differenced anyway. Any offseterrors in the single output buffer will be common to the readout of eachof the dual nodes. The error will be subtracted when the finaldifference is achieved. However, there could still be an advantage tothe double sampled read out sequence described. For example, anadvantage would be to subtract offsets induced by differences in theparasitic feed through from the clock signals applied to switches 126and 146 (parasitic feed through from the clocks applied to thoseswitches through to the source/drains).

In a first embodiment of the invention, a sensor includes controlcircuitry and a pixel having a photo site (110 of FIG. 1, 210 of FIG.2), a first storage node (120 of FIG. 1, 220 of FIG. 2) and a secondstorage node (140 of FIG. 1, 240 of FIG. 2). As will be appreciated fromthe disclosure herein, the control circuitry transfers a first collectedsignal from the photo site to the first storage node during a firstperiod, transfers a second collected signal from the photo site to thesecond storage node during a second period that follows the firstperiod, and then transfer the first and second collected signals out ofthe pixel during a third period that follows the second period.

FIG. 1 illustrates the charge transfer architecture. Signal charge istransferred from the photosite across two separate transfer gates to twoseparate storage capacitors. In another embodiment of the invention, inthe sensor described above, the photo site (110) includes a photodetector (112) where the photo detector is either a photodiode or apinned photodiode. The first and second collected signals are chargetype signals where the signal value is encoded by the number of chargeunits regardless of the potential that represents. Most sensorscollected photo electrons as the charge units; although, hole might becollected.

In yet another embodiment of the invention, in the sensor describedabove, the first storage node (120) includes a first charge holdingcapacitor (122) and a first charge transfer gate (124) coupled betweenthe first charge holding capacitor and the photo detector. The secondstorage node (140) includes a second charge holding capacitor (142) anda second charge transfer gate (144) coupled between the second chargeholding capacitor and the photo detector. A charge holding capacitorshould be understood to be a capacitor that holds a signal defined bythe charge held, in contrast to the voltage. Persons of ordinary skillin the art in light of these teachings will appreciate that the voltageon the capacitor is computed from a ratio of the charge held on thecapacitor divided by the capacitance. Suitable capacitors for thisapplication include reverse biased diodes.

In yet another embodiment of the invention, in the sensor describedabove, the pixel further includes an output buffer (162), and the firststorage node further includes an output voltage switch (126) coupledbetween the first charge holding capacitor and the output buffer. Thesecond storage node further includes an output voltage switch (146)coupled between the second charge holding capacitor and the outputbuffer. A preferred voltage switch for this application includes atransistor with a switching signal applied to the gate electrode withsufficient potential to totally turn on and turn off conduction throughthe transistor for all signal voltages in the range expected for signalsstored on the node's capacitor.

In another embodiment of the invention, in the sensor described above asa first embodiment, the photo site (110) includes a photo detector (112)where the photo detector is either a photodiode or a pinned photodiode.The first and second collected signals are charge type signals where thesignal value is encoded by the number of charge units regardless of thepotential that represents. Most sensors collected photo electrons as thecharge units; although, hole might be collected. In this embodiment, thepixel further includes an output buffer (162), and the first storagenode includes a first charge holding capacitor (122) and an outputvoltage switch (126) coupled between the first charge holding capacitorand the output buffer. The second storage node includes a second chargeholding capacitor (142) and an output voltage switch (146) coupledbetween the second charge holding capacitor and the output buffer.

In a second basic architecture, a voltage transfer architecture, thesignal is transferred from the charge domain to the voltage domainwithin the photosite. The photosite acts as a collection site for photogenerated electrons and as a sense node with a characteristiccapacitance through which the signal charges are converted to a voltage.The signal voltage is buffered before driving two distinctsample-and-hold capacitors as illustrated in FIG. 2.

FIG. 2 illustrates the buffered photosite architecture. Signal charge isconverted to a voltage on the photosite which is then buffered anddirected onto one of two sample-and-hold capacitors. In a secondembodiment of the invention, a sensor includes control circuitry and apixel having a photo site (210 of FIG. 2), a first storage node (220 ofFIG. 2) and a second storage node (240 of FIG. 2). As will beappreciated from the disclosure herein, the control circuitry transfersa first collected signal from the photo site to the first storage nodeduring a first period, transfers a second collected signal from thephoto site to the second storage node during a second period thatfollows the first period, and then transfer the first and secondcollected signals out of the pixel during a third period that followsthe second period. The photo site (210) includes a photo detector (212)and an input buffer (214) where the photo detector is either aphotodiode or a pinned photodiode. The first and second collectedsignals are voltage type signals where the signal value is encoded asthe voltage provided at the output of the photo site (210). Actually,the voltage at the output of the input buffer (214) is based on theconversion of charge to voltage on the capacitance of the sense node andadjusted for any voltage gain in the input buffer.

In another embodiment of the invention with voltage sample holdingcapacitors, in the sensor described above as a second embodiment, thefirst storage node (220) includes a first voltage sample holdingcapacitor (222) and an input voltage switch (224) coupled between theinput buffer and the first voltage sample holding capacitor. The secondstorage node (240) includes a second voltage sample holding capacitor(242) and an input voltage switch (244) coupled between the input bufferand the second voltage sample holding capacitor. The voltage switchesare as previously described. The voltage sample holding capacitor is acapacitance, as described below, that holds a signal value encoded as avoltage, and the capacitor operates over a sufficient voltage range tostore the range of expected signal values.

In another variant of the second embodiment of the invention with anoutput buffer, in the sensor described above as a second embodiment, thepixel further includes an output buffer (262), and the first storagenode (220) includes a first voltage sample holding capacitor (222), aninput voltage switch (224) coupled between the input buffer and thefirst voltage sample holding capacitor, and an output voltage switch(226) coupled between the first voltage sample holding capacitor and theoutput buffer. The second storage node (240) includes a second voltagesample holding capacitor (242), an input voltage switch (244) coupledbetween the input buffer and the second voltage sample holdingcapacitor, and an output voltage switch (246) coupled between the secondvoltage sample holding capacitor and the output buffer. The voltageswitches are as previously described. The voltage sample holdingcapacitor is a capacitance, as operates over a sufficient voltage rangeto store the range of expected signal values.

In another embodiment of the invention, in the sensor described above asa second embodiment, the pixel further includes an output buffer (262),and the first storage node includes a first voltage sample holdingcapacitor (222) and an output voltage switch (226) coupled between thefirst voltage sample holding capacitor and the output buffer. The secondstorage node includes a second voltage sample holding capacitor (242)and an output voltage switch (246) coupled between the second voltagesample holding capacitor and the output buffer.

The buffered scheme avoids having to transfer charge, something that isdifficult to do with low noise and low lag in CMOS proceses without PPDphotosites. This architecture also eliminates the need for a reset ofthe storage nodes. However, buffered architectures do require anadditional level of buffering in the pixel which consumes power, realestate on a chip in a monolithic semiconductor wafer, and reduces themaximum available signal swing range in the photo site due to the extraVT drop across the photo site buffer. There is also more read noise dueto additional buffer amplifier.

In a charge transfer architecture, when a conventional diode is used toproduce the photosite, then charge transfer is incomplete. This leads toimage lag and to FPN (fixed pattern noise) due to transistor thresholdVT variations between the two different transfer gates. One solution isto implement the photosite as a pinned photodiode (PPD) which allows thephotosite to be fully depleted during charge transfer therebyeliminating lag and eliminating sensitivity to VT variations.

Another solution is to arrange the biasing/clocking in such a way as toshare charge between the photosite and the storage capacitor duringintegration. This is accomplished by maintaining the transfer gate at ahigh level during the integration so that the incoming charge is sharedbetween the photosite capacitor and storage capacitor to produce acommon voltage level. At the end of integration, the transfer gate isclocked to its low level to isolate the photosite and storagecapacitors. The charge sharing scheme works well if the photosite can beseparately pre-reset to a known voltage level before integration begins.

In another embodiment of the invention, a sensor includes controlcircuitry and a pixel having a photo site (110 of FIG. 1), a firststorage node (120 of FIG. 1) and a second storage node (140 of FIG. 1).As will be appreciated from the disclosure herein, the control circuitrytransfers a first collected signal from the photo site to the firststorage node during a first period, transfers a second collected signalfrom the photo site to the second storage node during a second periodthat follows the first period, and then transfer the first and secondcollected signals out of the pixel during a third period that followsthe second period. The photo site (110) includes a photo detector (112)where the photo detector is either a photodiode or a pinned photodiode.The first and second collected signals are charge type signals where thesignal value is encoded by the number of charge units regardless of thepotential that represents. The first storage node (120) includes a firstcharge holding capacitor (122) and a first charge transfer gate (124)coupled between the first charge holding capacitor and the photodetector. The second storage node (140) includes a second charge holdingcapacitor (142) and a second charge transfer gate (144) coupled betweenthe second charge holding capacitor and the photo detector. The controlcircuitry is coupled to the first charge transfer gate (124) to providea first control signal that can enable charges to freely transferbetween the photo detector (112) and the first charge holding capacitor(122) throughout the first period, and the control circuitry is alsocoupled to the second charge transfer gate (144) to provide a secondcontrol signal that can enable charges to freely transfer between thephoto detector (112) and the second charge holding capacitor (142)throughout the second period.

For anti-blooming and exposure control functionality, the pixel in FIG.1 includes a separate gate, off of the photo site, that allows the photosite to be reset or preset. This switch does not otherwise need to beincluded since the photo site does not have to be explicitly reset. Itis implicitly reset by virtue of the charge transfer operation. However,if a photo site preset gate is provided, then one can allow foranti-blooming (AB) during a frame read. A storage capacity of the photodetector (photodiode or PPD) might be sized for complete filling withphoto charge without blooming by a short exposure with intense lightduring an exposure interval. However, were the same intensity of lightto fall on the photo detector during a longer readout time the photogenerated charges would otherwise fill the photo site and spill into thestorage nodes thereby corrupting the stored charge packet during theframe readout. The gate also allows the photo site to be reset directlybefore the start of an integration period rather than indirectly byclocking the transfer gate (often referred to as the TCK gate) while thestorage node reset gate is active. The gate also allows the photo siteto be ‘hard reset’ (VPR set to a lower voltage than the high level onthe reset switch minus a VT) in order to eliminate image lag for a photosite constructed with a conventional diode that cannot be fullydepleted. Note though that the ‘hard’ reset can also be accomplished viaother reset gates in the pixel that will be discussed next if having anon-overlap between the integration period and readout period for theprevious frame can be tolerated. Note that VPR can be set to VDD inorder to save a bus line. This eliminates the option of doing a hardreset on the photosite, but it still allows for exposure control andanti-blooming.

In another basic charge transfer embodiment of the invention with presetgate, a sensor includes control circuitry and a pixel having a photosite (110 of FIG. 1), a first storage node (120 of FIG. 1) and a secondstorage node (140 of FIG. 1). As will be appreciated from the disclosureherein, the control circuitry transfers a first collected signal fromthe photo site to the first storage node during a first period,transfers a second collected signal from the photo site to the secondstorage node during a second period that follows the first period, andthen transfer the first and second collected signals out of the pixelduring a third period that follows the second period. The photo site(110) includes a photo detector (112) where the photo detector is eithera photodiode or a pinned photodiode. The first and second collectedsignals are charge type signals where the signal value is encoded by thenumber of charge units regardless of the potential that represents. Thephoto site (110) further includes a preset gate (116) coupled to thephoto detector (112), and the control circuitry is coupled to the presetgate to provide the preset gate with a preset signal (VPR).

In another embodiment of the invention, in the sensor described above inthe basic charge transfer embodiment of the invention with preset gate,the control circuitry is coupled to the preset gate (116) to provide apreset gate control signal to a gate electrode of the preset gate, andthe control circuitry controls a potential of the preset signal to beless than a potential of the preset gate control signal minus atransistor threshold voltage VT, at least for a moment to achieve a hardreset. This provides a basic hard reset capability. In a variant, thepotential of the preset gate control signal differs from the potentialof the preset signal by the transistor threshold voltage.

In another embodiment of the invention, in the sensor described above inthe basic charge transfer embodiment of the invention with preset gate,the control circuitry is coupled to the preset gate to provide thepreset gate with a preset signal (VPR) at a potential that operates as adrain, and the control circuitry is coupled to the preset gate (116) toprovide a preset gate control signal at a potential that enables thepreset gate to transfer a quantity of charge into the preset signal whenaccumulated charges in the photo detector (112) exceed a capacity of thephoto detector to hold charge. This provides a basic anti-bloomingfunction since charge in excess of the photo detector's capacity to holdcharge with be shunted and drained away by the preset signal VPR. Thephoto detector is a photo diode or pinned photo diode characterized by acapacitance that is primarily defined by the diode area and dopantconcentration. When the diode is reset, the diode “capacitance” ischarged positively relative to the substrate. The capacity to hold photoelectrons is substantially defined by the number of photo electrons thatwould change the potential in the diode to be substantially equal to thepotential of the substrate (or other adjacent or near by region thatmight be subject to cross contamination).

In another embodiment of the invention, in the sensor described above inthe basic charge transfer embodiment of the invention with preset gate,the control circuitry is coupled to the preset gate to provide thepreset gate with the preset signal (VPR) at a potential that operates asa drain, and the control circuitry is also coupled to gate electrode ofthe preset gate (116) to provide a preset gate control signal. Thecontrol circuitry provides the preset gate control signal during a firstportion of the first period at a first potential that enables the presetgate to transfer substantially all photo generated charge into thepreset signal (thus acting like a shutter by preventing the accumulationof photo charge), and the control circuitry provides the preset gatecontrol signal during a second portion of the first period at a secondpotential that enables the preset gate to transfer a quantity of chargeinto the preset signal when accumulated charges in the photo detector(112) exceed a capacity of the photo detector to hold charge (thusperforming an anti-blooming function).

In another basic voltage transfer embodiment of the invention withpreset gate, a sensor includes control circuitry and a pixel having aphoto site (210 of FIG. 2), a first storage node (220 of FIG. 2) and asecond storage node (240 of FIG. 2). As will be appreciated from thedisclosure herein, the control circuitry transfers a first collectedsignal from the photo site to the first storage node during a firstperiod, transfers a second collected signal from the photo site to thesecond storage node during a second period that follows the firstperiod, and then transfer the first and second collected signals out ofthe pixel during a third period that follows the second period. Thephoto site (210) includes a photo detector (212) where the photodetector is either a photodiode or a pinned photodiode. The first andsecond collected signals are voltage type signals where the signal valueis encoded in the voltage regardless of the number of charge units thatrepresents on a particular capacitor. The photo site (210) furtherincludes a preset gate (216) coupled to the photo detector (212), andthe control circuitry is coupled to the preset gate to provide thepreset gate with a preset signal (VPR).

In another embodiment of the invention, in the sensor described above inthe basic voltage transfer embodiment of the invention with preset gate,the photo detector (212) is a photodiode, the control circuitry iscoupled to a gate electrode of the preset gate (216) to provide a presetgate control signal, and the control circuitry controls a potential ofthe preset signal to be less than a potential of the preset gate controlsignal minus a transistor threshold voltage VT, at least for a moment toachieve a hard reset. This provides a basic hard reset capability. In avariant, the potential of the preset gate control signal differs fromthe potential of the preset signal by the transistor threshold voltage.In a variant, the potential of the preset gate control signal differsfrom the potential of the preset signal by the transistor thresholdvoltage.

In another embodiment of the invention, in the sensor described above inthe basic voltage transfer embodiment of the invention with preset gate,the control circuitry is coupled to the preset gate to provide thepreset gate with a preset signal (VPR) at a potential that operates as adrain, and the control circuitry is coupled to the preset gate (216) toprovide a preset gate control signal at a potential that enables thepreset gate to transfer a quantity of charge into the preset signal whenaccumulated charges in the photo detector (212) exceed a capacity of thephoto detector to hold charge (thus performing an anti-bloomingfunction).

In another embodiment of the invention, in the sensor described above inthe basic voltage transfer embodiment of the invention with preset gate,the control circuitry is coupled to the preset gate to provide thepreset gate with a preset signal (VPR) at a potential that operates as adrain, and the control circuitry is coupled to a gate electrode of thepreset gate (216) to provide a preset gate control signal. The controlcircuitry provides the preset gate control signal during a first portionof the first period at a first potential that enables the preset gate totransfer substantially all photo generated charge into the preset signal(thus acting like a shutter by preventing the accumulation of photocharge); and the control circuitry provides the preset gate controlsignal during a second portion of the first period at a second potentialthat enables the preset gate to transfer a quantity of charge into thepreset signal when accumulated charges in the photo detector (212)exceed a capacity of the photo detector to hold charge (thus performingan anti-blooming function).

For storage node reset, the pixel circuitry must allow for the resettingof the storage nodes before charge is transferred from the photosite. Itshould also allow for the resetting of the parasitic load capacitance ofthe input to the buffer that drives the column data line. Severaloptions for the location of the reset switch are illustrated in FIG. 3.In general, not all of these will be included in a given pixel design.

FIG. 3 illustrates possible locations for the reset switches for thephotosite/storage node/buffer input. Storage node reset can beaccomplished separately by Reset #1 and Reset #2. If it is acceptable toreset both nodes at the same time (more on this in section on FPNreduction) then the same clock can be applied to Reset #1 and Reset #2in order to save a bus line. Ideally, the biases applied to the drainsof the reset switches are arranged so that there is a ‘hard’ reset ofthe relevant nodes in order to eliminate lag and to eliminatesensitivity to variations in the VT beneath of the relevant reset FET's.

In another basic charge transfer embodiment of the invention with resetgates for the nodes, a sensor includes control circuitry and a pixelhaving a photo site (110 of FIG. 1), a first storage node (120 ofFIG. 1) and a second storage node (140 of FIG. 1). As will beappreciated from the disclosure herein, the control circuitry transfersa first collected signal from the photo site to the first storage nodeduring a first period, transfers a second collected signal from thephoto site to the second storage node during a second period thatfollows the first period, and then transfer the first and secondcollected signals out of the pixel during a third period that followsthe second period. The photo site (110) includes a photo detector (112)where the photo detector is either a photodiode or a pinned photodiode.The first and second collected signals are charge type signals where thesignal value is encoded by the number of charge units regardless of thepotential that represents. The first storage node (120) includes a firstcharge holding capacitor (122), a first charge transfer gate (124)coupled between the first charge holding capacitor and the photodetector, and a first reset gate (128) coupled to the first chargeholding capacitor (122). The second storage node (140) includes a secondcharge holding capacitor (142), a second charge transfer gate (144)coupled between the second charge holding capacitor and the photodetector, and a second reset gate (148) coupled to the second chargeholding capacitor (142). A charge holding capacitor should be understoodto be a capacitor that holds a signal defined by the charge held, incontrast to the voltage.

In another embodiment of the invention, in the sensor described above inthe basic charge transfer embodiment of the invention with reset gatesfor the nodes, the first reset gate (128) is coupled between the firstcharge holding capacitor (122) and a first reset signal. The controlcircuitry is coupled to the first reset gate (128) of the first storagenode to provide a first reset gate control signal, and the controlcircuitry controls a potential of the first reset signal to be less thana potential of the first reset gate control signal minus a transistorthreshold voltage VT. In a variant, the potential of the first resetgate control signal differs from the potential of the first reset signalby the transistor threshold voltage.

The input to the column buffer will have a non-zero parasiticcapacitance which ideally should also be reset. This can be accomplishedwith Reset #3. Again, a hard reset is preferred. Ideally the reset levelon the input to the column amplifier is identical to the reset levels onthe storage nodes. Reset #3 can be eliminated, or the Resets #1 and/or#2 for the storage nodes can be eliminated if the reset operation isperformed with the switches that connect the storage nodes to the bufferare turned on during the reset operation.

In another basic charge transfer embodiment of the invention with areset gate at the output buffer, a sensor includes control circuitry anda pixel having a photo site (110 of FIG. 1), a first storage node (120of FIG. 1), a second storage node (140 of FIG. 1), and an output buffer(162). As will be appreciated from the disclosure herein, the controlcircuitry transfers a first collected signal from the photo site to thefirst storage node during a first period, transfers a second collectedsignal from the photo site to the second storage node during a secondperiod that follows the first period, and then transfer the first andsecond collected signals out of the pixel during a third period thatfollows the second period. The photo site (110) includes a photodetector (112) where the photo detector is either a photodiode or apinned photodiode. The first and second collected signals are chargetype signals where the signal value is encoded by the number of chargeunits regardless of the potential that represents. The first storagenode includes a first charge holding capacitor (122) and an outputvoltage switch (126) coupled between the first charge holding capacitorand the output buffer, and the second storage node includes a secondcharge holding capacitor (142) and an output voltage switch (146)coupled between the second charge holding capacitor and the outputbuffer. The sensor further includes a reset gate (160) coupled betweenan input of the output buffer (162) and a reset signal. The controlcircuitry is coupled to a gate electrode of the reset gate (160) toprovide a reset gate control signal, and the control circuitry controlsa potential of the reset signal to be less than a potential of the resetgate control signal minus a threshold voltage. This provides a hardreset function. In a variant, the potential of the reset gate controlsignal differs from the potential of the reset signal by a transistorthreshold voltage VT.

In another embodiment of the invention, a sensor includes controlcircuitry and a pixel having a photo site (110 of FIG. 1), a firststorage node (120 of FIG. 1) and a second storage node (140 of FIG. 1).As will be appreciated from the disclosure herein, the control circuitrytransfers a first collected signal from the photo site to the firststorage node during a first period, transfers a second collected signalfrom the photo site to the second storage node during a second periodthat follows the first period, and then transfer the first and secondcollected signals out of the pixel during a third period that followsthe second period. The photo site (110) includes a photo detector (112)where the photo detector is either a photodiode or a pinned photodiode.The first and second collected signals are charge type signals where thesignal value is encoded by the number of charge units regardless of thepotential that represents. The first storage node (120) includes a firstcharge holding capacitor (122) and a first charge transfer gate (124)coupled between the first charge holding capacitor and the photodetector. The second storage node (140) includes a second charge holdingcapacitor (142) and a second charge transfer gate (144) coupled betweenthe second charge holding capacitor and the photo detector. The sensorfurther includes a first output buffer (162) coupled to the first chargeholding capacitor (122), a first row switch (164) coupled between thefirst output buffer and a first column bus (166), a second output buffer(172) coupled to the second charge holding capacitor (142), and a secondrow switch (174) coupled between the second output buffer and a secondcolumn bus (176).

In another basic voltage transfer embodiment of the invention with dualoutput buffers, a sensor includes control circuitry and a pixel having aphoto site (210 of FIG. 2), a first storage node (220 of FIG. 2) and asecond storage node (240 of FIG. 2). As will be appreciated from thedisclosure herein, the control circuitry transfers a first collectedsignal from the photo site to the first storage node during a firstperiod, transfers a second collected signal from the photo site to thesecond storage node during a second period that follows the firstperiod, and then transfer the first and second collected signals out ofthe pixel during a third period that follows the second period. Thephoto site (210) includes a photo detector (212) where the photodetector is either a photodiode or a pinned photodiode. The first andsecond collected signals are voltage type signals where the signal valueis encoded in the voltage regardless of the number of charge units thatrepresents on a particular capacitor. The first storage node (220)includes a first voltage sample holding capacitor (222) and an inputvoltage switch (224) coupled between the input buffer and the firstvoltage sample holding capacitor, and the second storage node (240)includes a second voltage sample holding capacitor (242) and an inputvoltage switch (244) coupled between the input buffer and the secondvoltage sample holding capacitor. The sensor further includes a firstoutput buffer (262) coupled to the first voltage sample holdingcapacitor (222), a first row switch (264) coupled between the firstoutput buffer and a first column bus (266), a second output buffer (272)coupled to the second voltage sample holding capacitor (242), and asecond row switch (274) coupled between the second output buffer and asecond column bus (276).

These Reset #1 and/or #2 and/or #3 can even be used to do a hard resetof the photosite as long as the biases and switches are clocked so thatthe reset level on the photosite is lower than the reset levels on thestorage nodes (need to be able to subsequently transfer charge out ofthe photosite). In this case the photosite reset operation has to occurafter the previous frame has been read out which means that integrationcannot occur in parallel with the readout of the previously capturedframe. It also means that there can be no antiblooming during readout.This reset would be performed by clocking the bias on the drain of Reset#1, #2, or #3 to a low level with all switches and transfer gates on tohard reset the photosite to a low voltage. The bias on the drain wouldthen be clocked high causing the photosite to spill excess charge to thechannel potential beneath each of the transfer gates (also therebyeliminating sensitivity to VT differences on the two gates).

All storage node resetting can equivalently be done by VPR and thephotosite reset switch, but again the photosite reset operation has tooccur after the previous frame has been read out which means thatintegration cannot occur in parallel with the readout of the previouslycaptured frame. In that case the photosite transfer gates need to have 3clock levels. During the storage node resets these gates are clocked totheir highest levels and VPR is kept at a high voltage. Subsequently,the transfer gates are clocked to a medium level at which they sitduring a photosite transfer thereby resetting the photosite. Followingthe reset the transfer gates are clocked to a low level to allow forintegration.

As noted above, the photosite does not need to be explicitly reset inorder to operate. The photosite is implicitly reset every time charge istransferred across one of the TCK gates (transfer gates). Generally thephotosite will need to be reset, explicitly or implicitly, before thestart of integration in order to provide a known starting point. If thephotosite is a PPD, then the most straightforward reset method is notvia the TCK gates, but rather via the antiblooming gate on thephotosite.

If the photosite is implemented as a conventional photodiode, then thepreferred reset method is as follows. First the AB gate is pulsed insuch a way as to hard reset the photosite. Then, the TCK1 gate is pulsedto reset the photosite to the level of the transfer gate. Then, theintegration is performed. After integration, the charge is transferredvia TCK1 to storage node #1. The photosite is again hard reset via theAB gate, then soft reset across the TCK2 gate, then the secondintegration takes place, then the accumulated charge is transferred tothe storage node #2. This reset sequence eliminates image lag in thephotosite (hard reset), and also eliminates both fat zero noise andsensitivity to VT mismatch between the two TCK gates in the pixel.

To soft reset the photosite across a preset gate, the voltage VPR is setto a positive drain voltage to draw photo electrons, and a preset gatecontrol signal applied to the gate electrode of the preset gate is setto a preset voltage. Photoelectrons are drawn across the preset gatetoward the voltage VPR until the voltage on the photo detector is avoltage threshold VT below the voltage of the preset gate controlsignal, the preset voltage. Unfortunately, the final photo detectorvoltage is actually a function of not only the gate's VT, but also theinitial charge in the photo detector and the duration of the transferleading to image lag.

(VPR Set to a Lower Voltage than the High Level on the Reset SwitchMinus a VT)

A hard reset procedure eliminates some of the uncertainty of the softreset procedure. To hard reset the photo site across a preset gate, thepreset voltage VPR is set to a first voltage level desired for the photodetector at a beginning of the integration cycle, and a preset gatecontrol signal is applied to the gate electrode of the preset gate isset to a more positive voltage (e.g., than the preset voltage) to allowelectrons from VPR to transfer into the photo detector. When the presetsignal VPR is later switched to a more positive voltage level, electronsno longer transfer across the preset gate into the photo detector.However, photo electrons are generated during the integration cycle tomake the potential on the photo detector more negative according to theamount of light detected. If a soft reset were to immediately follow thehard reset, voltage VPR is switched to a more positive voltage to beused as a drain. Any excess electrons in the photo detector that causethe photo detector to be at a potential more negative than the presetgate control signal applied to the gate electrode of the preset gate(minus the transistor threshold voltage VT) are drained off into thepreset signal VPR. In the soft reset step, the extra electronstransferred to the photo detector during a hard reset (that make thepotential of the photo detector more negative than the preset gatecontrol signal) are drained into the voltage VPR. The photo detector isleft at a potential equal to the preset voltage minus VT regardless ofwhether any charge remains in the photo detector from a previousintegration cycle, thus eliminating image lag.

The pixel can be configured with one or two data columns. With a singlecolumn the column is used at different times to output each of the twostorage nodes. An advantage of this architecture is that the columnbuffer, column, and column amplifier can be common for the two nodesthereby eliminating mismatch issues.

FIG. 4 illustrates a dual node pixel with two output data columns. Apixel with two data columns can be more appropriate for certaindifferencing amplifiers (in the illustrated pixels the differencing ampsare located off-array). In this case the pixel will generally beconfigured with two identical column buffers as illustrated in FIG. 4.This architecture allows the two signals to be available at the sametime for off-array processing (e.g. can be fed simultaneously into adifference amplifier). With the dual output there is no need toseparately reset the node attached to the column buffer since there isno switch between the buffer input and the storage node.

As with conventional CMOS imager pixels, there will be fixed patternnoise (FPN) from pixel-to-pixel differences in the DC offset levels forthe gates and amplifiers. In most conventional pixels this “noise” isreduced by double sampling whereby the signal level is put on the columnand sampled, and then the pixel is reset and the operation is repeated.The output signal is the difference between these two samples. Ideallythe same concepts will be applied to a dual node pixel.

Where the pixel is configured with a single data column and columnbuffer, then the differencing takes place when the two signal from thetwo nodes are differenced off-array. Any offset variations from pixel topixel in the column buffer will be applied equally to the two signals.

When two separate data columns and two separate column buffers are used,then each of the nodes are sampled with the signals and then again aftera reset. In particular, for each node read, the signal on the node wouldbe put on the appropriate column bus, then the storage node would bereset, then that reset level would be buffered onto the data column. Thedifference between the signal and reset level eliminates any offseterrors in the column buffers. The differencing does not eliminatemismatch errors between the TCK gates. A way to eliminate that type oferror is via a PPD photosite (i.e., a photosite that can be fullydepleted). However, an alternative way to remove mismatch between thetransfer gates, as described elsewhere, has a penalty that the imageintegration can't begin until after the prior frame has been read out.For most applications, the PPD implementation is preferred.

The simplest pixel configuration is to implement all of the circuitry inNMOS or PMOS. However, there can be advantages to mixing both PMOS andNMOS within the same pixel. For example, if the reset gates #1, #2, and#3 in FIG. 3 are implemented in PMOS and the TCK gates and photositepreset gate are implemented in NMOS, then the storage sites can be resetto the most positive power rail thereby providing more potential swingfor the column buffers (in this case would be implemented in NMOS),something that is attractive for low voltage processes. Persons ofordinary skill in the art will appreciate in light of these teachingsthat sensors that are implemented in NMOS technology (n typeconductivity drains and sources formed in p type material) can beredesigned and implemented in PMOS technology (p type conductivitydrains and sources formed in n type material) and vice versa. Mixing thetwo technologies provides additional advantages as discussed herein.

A drawback of the buffered photosite architecture (voltage transferarchitecture) is voltage drops within the pixel due to the buffer willtend to reduce the range available for signal swings. If both thephotosite buffer and the column driver are implemented as NMOSsource-followers, then there will be at least two VT drops, one acrossthe first buffer and the other across the second buffer. Those two dropscan consume so much of the available rail-to-rail voltage as to leave aninsufficiently small range for signal swing.

One solution is to implement the two in-pixel buffers in oppositepolarity (e.g., the photosite buffer as an NMOS source-follower and thecolumn buffer as a PMOS source-follower). The negative offset induced bythe first buffer will be largely offset by the positive offset of thesecond buffer. Similarly, the reset FET on the photosite could beimplemented in a different polarity in order to move the reset levelcloser to the applicable rail.

In a variant of a basic charge transfer embodiment of the invention withdual nodes, a sensor includes control circuitry and a pixel having aphoto site (110 of FIG. 1), a first storage node (120 of FIG. 1) and asecond storage node (140 of FIG. 1). As will be appreciated from thedisclosure herein, the control circuitry transfers a first collectedsignal from the photo site to the first storage node during a firstperiod, transfers a second collected signal from the photo site to thesecond storage node during a second period that follows the firstperiod, and then transfer the first and second collected signals out ofthe pixel during a third period that follows the second period. Thephoto site (110) includes a photo detector (112) where the photodetector is either a photodiode or a pinned photodiode. The first andsecond collected signals are charge type signals where the signal valueis encoded by the number of charge units regardless of the potentialthat represents. The first storage node (120) includes a first chargeholding capacitor (122), a first charge transfer gate (124) coupledbetween the first charge holding capacitor and the photo detector, and areset gate (128) coupled to the first charge holding capacitor (122),and the second storage node (140) includes a second charge holdingcapacitor (142), a second charge transfer gate (144) coupled between thesecond charge holding capacitor and the photo detector, and a reset gate(148) coupled to the second charge holding capacitor (142). In onevariant, the first and second charge transfer gates are formed of NMOStechnology, and the reset gates of the first and second storage nodesare formed of PMOS technology. In another variant, the first and secondcharge transfer gates are formed of PMOS technology, and the reset gatesof the first and second storage nodes are formed of NMOS technology.

In another variant of a basic charge transfer embodiment of theinvention with dual nodes, a sensor includes control circuitry and apixel having a photo site (110 of FIG. 1), a first storage node (120 ofFIG. 1), a second storage node (140 of FIG. 1), an output buffer (162),and a reset gate coupled to an input of the output buffer. As will beappreciated from the disclosure herein, the control circuitry transfersa first collected signal from the photo site to the first storage nodeduring a first period, transfers a second collected signal from thephoto site to the second storage node during a second period thatfollows the first period, and then transfer the first and secondcollected signals out of the pixel during a third period that followsthe second period. The photo site (110) includes a photo detector (112)where the photo detector is either a photodiode or a pinned photodiode.The first and second collected signals are charge type signals where thesignal value is encoded by the number of charge units regardless of thepotential that represents. The first storage node (120) includes a firstcharge holding capacitor (122), a first charge transfer gate (124)coupled between the first charge holding capacitor and the photodetector, and an output voltage switch (126) coupled between the firstcharge holding capacitor and the output buffer, and the second storagenode (140) includes a second charge holding capacitor (142), a secondcharge transfer gate (144) coupled between the second charge holdingcapacitor and the photo detector, and an output voltage switch (146)coupled between the second charge holding capacitor and the outputbuffer. In one variant, the reset gate coupled to an input of the outputbuffer is formed of PMOS technology, and the first and second chargetransfer gates are formed of NMOS technology. In another variant, thereset gate coupled to an input of the output buffer is formed of NMOStechnology, and the first and second charge transfer gates are formed ofPMOS technology.

In another basic charge transfer embodiment of the invention with presetgate, a sensor includes control circuitry and a pixel having a photosite (110 of FIG. 1), a first storage node (120 of FIG. 1) and a secondstorage node (140 of FIG. 1). As will be appreciated from the disclosureherein, the control circuitry transfers a first collected signal fromthe photo site to the first storage node during a first period,transfers a second collected signal from the photo site to the secondstorage node during a second period that follows the first period, andthen transfer the first and second collected signals out of the pixelduring a third period that follows the second period. The photo site(110) includes a photo detector (112) and a preset gate (116) coupled tothe photo detector (112). The photo detector is either a photodiode or apinned photodiode. The first and second collected signals are chargetype signals where the signal value is encoded by the number of chargeunits regardless of the potential that represents. The control circuitryis coupled to the preset gate to provide the preset gate with a presetsignal (VPR). The first storage node (120) includes a first chargeholding capacitor (122) and a first charge transfer gate (124) coupledbetween the first charge holding capacitor and the photo detector, andthe second storage node (140) includes a second charge holding capacitor(142) and a second charge transfer gate (144) coupled between the secondcharge holding capacitor and the photo detector. In one variant, thefirst and second charge transfer gates are formed of NMOS technology,and the preset gate is formed of PMOS technology. In another variant,the first and second charge transfer gates are formed of PMOStechnology, and the preset gate is formed of NMOS technology.

In another basic voltage transfer embodiment of the invention withpreset gate, a sensor includes control circuitry and a pixel having aphoto site (210 of FIG. 2), a first storage node (220 of FIG. 2) and asecond storage node (240 of FIG. 2). As will be appreciated from thedisclosure herein, the control circuitry transfers a first collectedsignal from the photo site to the first storage node during a firstperiod, transfers a second collected signal from the photo site to thesecond storage node during a second period that follows the firstperiod, and then transfer the first and second collected signals out ofthe pixel during a third period that follows the second period. Thephoto site (210) includes a photo detector (212) and a preset gate (216)coupled to the photo detector. The photo detector is either a photodiodeor a pinned photodiode. The first and second collected signals arevoltage type signals where the signal value is encoded in the voltageregardless of the number of charge units that represents on a particularcapacitor. The control circuitry is coupled to the preset gate toprovide the preset gate with a preset signal (VPR). In one variant, thepreset gate is formed of NMOS technology, and the input buffer is formedof PMOS technology. In another variant, the preset gate is formed ofPMOS technology, and the input buffer is formed of NMOS technology.

In another basic voltage transfer embodiment of the invention with anoutput buffer, a sensor includes control circuitry and a pixel having aphoto site (210 of FIG. 2), a first storage node (220 of FIG. 2), asecond storage node (240 of FIG. 2), and an output buffer (262). As willbe appreciated from the disclosure herein, the control circuitrytransfers a first collected signal from the photo site to the firststorage node during a first period, transfers a second collected signalfrom the photo site to the second storage node during a second periodthat follows the first period, and then transfer the first and secondcollected signals out of the pixel during a third period that followsthe second period. The photo site (210) includes a photo detector (212)where the photo detector is either a photodiode or a pinned photodiode.The first and second collected signals are voltage type signals wherethe signal value is encoded in the voltage regardless of the number ofcharge units that represents on a particular capacitor. The firststorage node includes a first voltage sample holding capacitor (222) andan output voltage switch (226) coupled between the first voltage sampleholding capacitor and the output buffer, and the second storage nodeincludes a second voltage sample holding capacitor (242) and an outputvoltage switch (246) coupled between the second voltage sample holdingcapacitor and the output buffer. In one variant, the input buffer isformed of PMOS technology, and the output buffer is formed of NMOStechnology. In another variant, the input buffer is formed of NMOStechnology, and the output buffer is formed of PMOS technology.

Another solution makes use of parasitic overlap capacitances to inducefeedthroughs with a polarity that counteracts the VT drops within thepixel. This is a bootstrapping scheme. For example, the pixel in FIG. 5is configured with an NMOS photosite buffer and two NMOS column buffers.During the storage of the signals on the storage nodes (Capacitor #1 andCapacitor #2) the bias VD is maintained at a low level. For readout, thebias VD is clocked high which turns on the column buffers. The low tohigh transition of the bias VD also causes the floating storage nodes tobe pulled up due to parasitic overlap capacitance between the VD nodeand the gate node of each source-follower. This induces a positiveoffset on the storage nodes which reduces the size of the VT dropbetween the photosite and the storage nodes.

In another variant of the second embodiment of the invention with anoutput buffer bootstrap, in the sensor described above as a secondembodiment, the pixel further includes an output buffer (262) thatincludes a source follower having drain and having a gate electrode asan input of the output buffer. The source follower is formed so that aparasitic capacitance exists between the drain and the gate electrode.The first storage node (220) includes a first voltage sample holdingcapacitor (222), an input voltage switch (224) coupled between the inputbuffer and the first voltage sample holding capacitor, and an outputvoltage switch (226) coupled between the first voltage sample holdingcapacitor and the output buffer. The second storage node (240) includesa second voltage sample holding capacitor (242), an input voltage switch(244) coupled between the input buffer and the second voltage sampleholding capacitor, and an output voltage switch (246) coupled betweenthe second voltage sample holding capacitor and the output buffer. Thevoltage switches are as previously described. The voltage sample holdingcapacitor is a capacitance, as operates over a sufficient voltage rangeto store the range of expected signal values. The control circuitry iscoupled to the drain of the source to provide a drain voltage signal,and the control circuitry includes logic that can control the drainvoltage signal to switch from one potential to another at a time ofreadout to induce a voltage through the parasitic capacitance that isadditive to a signal voltage applied to the gate electrode at the timeof readout. By proper adjustment of the voltage shift and the parasiticcapacitance, the consequences of transistor threshold voltage VT dropscan be compensated for.

FIG. 5 illustrates an implementation of buffered photosite architecture.The complication with the use of the parasitic overlap capacitancescheme is that there will be mismatch between the parasitic overlapcapacitances between two drain and storage nodes which will lead toslightly different offsets between the two outputs. This can beeliminated by instead using a single output column and single outputbuffer per pixel as illustrated in FIG. 6. As with the similar pixelimplemented with photosite charge transfer, this pixel requires switchesto connect the appropriate storage node to the output buffer, and anadditional reset switch so that the input node of the column buffer canbe reset. This implementation, of course, eliminates issues related togain mismatch between the two column buffers. FIG. 6 illustrates animplementation of buffered photosite architecture with single outputdata column.

The photosite requires a distinct reset gate since there is no other wayto remove the signal charge integrated from the photosite. If thephotosite is a PPD, then the photosite is fully depleted of chargeduring charge transfer to a storage node thereby eliminating kTC noise.If the photosite is a conventional diode then the easiest reset schemein terms of biasing and clocking is a soft one; however, a soft schemewill leave the pixel sensitive to lag and there will be a difference inthe reset level from pixel to pixel. A hard reset scheme will eliminatelag and will eliminate pixel to pixel variations in the reset level.

For the charge transfer architecture it is most desirable to minimizethe capacitance on the storage nodes since these nodes also double asthe “sense node” on which the signal charge is converted to a signalvoltage. Less capacitance translates to a high voltage swing for a givencharge signal, and it also reduces reset noise (kTC). For the bufferedphotosite implementation, the storage capacitors are storing a signalencoded as a certain voltage rather than a signal encoded as a certainamount of charge and hence these capacitances should be maximized inorder to minimize noise on the sampled voltage that is stored on them.Large capacitors can be implemented as large area diodes; however, theselarge area diodes will also act as sinks for charge photo generatedbeneath depletion region that lies beneath the photosite. When thischarge ends up migrating into the storage diodes, it shows up in thesignal as undesirable signal crosstalk. However, if the storagecapacitors are implemented as poly-on-poly or metal-on-metal capacitors(common elements in analog processes) then the capacitances can be madelarge while still maintaining a minimum sized diode thereby reducingcrosstalk.

In another embodiment of the invention with large storage capacitors, inthe sensor described above as a second embodiment, the first storagenode (220) includes a first voltage sample holding capacitor (222) andan input voltage switch (224) coupled between the input buffer and thefirst voltage sample holding capacitor. The second storage node (240)includes a second voltage sample holding capacitor (242) and an inputvoltage switch (244) coupled between the input buffer and the secondvoltage sample holding capacitor. The voltage switches are as previouslydescribed. The voltage sample holding capacitor is a capacitance, asdescribed below, that holds a signal value encoded as a voltage, and thecapacitor operates over a sufficient voltage range to store the range ofexpected signal values. The first voltage sample holding capacitor (222)is one of a poly-on-poly capacitor and a metal-on-metal capacitor, andthe second voltage sample holding capacitor (242) is one of apoly-on-poly capacitor and a metal-on-metal capacitor.

Though not specific to the buffered photosite implementation, theinternal pixel biases that run the in-pixel source-followers can beclocked so that they are operational only during the portions of theframe time that the source-followers need to be operational. Forexample, the bias voltage at the bottom of the photosite buffer wouldnormally be ground, but it can be clocked to VDD (or simply leftfloating) in order to eliminate current flow during the readout of thestorage nodes. In one scheme, the bootstrapping and power savefunctionalities can be combined such that the bias to the base of thephotosite buffer and to the top of the column buffers is shared. Thebias is low during the photosite read and high during the storage noderead. As the bias clocks from low to high at the end of the photositereads, then the stored voltages are increased.

In another embodiment of the invention with a power save feature, in thesensor described above as a second embodiment, the first storage node(220) includes a first voltage sample holding capacitor (222) and aninput voltage switch (224) coupled between the input buffer and thefirst voltage sample holding capacitor. The second storage node (240)includes a second voltage sample holding capacitor (242) and an inputvoltage switch (244) coupled between the input buffer and the secondvoltage sample holding capacitor. The voltage switches are as previouslydescribed. The voltage sample holding capacitor is a capacitance, asdescribed below, that holds a signal value encoded as a voltage, and thecapacitor operates over a sufficient voltage range to store the range ofexpected signal values. The control circuitry is coupled to the inputbuffer (214) to provide a drain signal and a source signal, and thecontrol circuitry clocks the drain and source signals to be operationalonly when charge in the photo detector (212) is read into one of thefirst voltage sample holding capacitor (222) and the second voltagesample holding capacitor (242).

In alternative embodiments of the invention, the invention isimplemented with either the charge transfer or the buffered photositearchitecture. The invention covers the mode of operation rather than tothe specific architecture. In the invention the signal is stored on onestorage site and the crosstalk signal equally stored on the two storagesites. Prior to the start of signal integration the signals on the twostorage nodes are reset. The signal is then integrated on the photosite.At the end of the integration period it is transferred to the firststorage node. The storage nodes are laid out symmetrically about thephotosite. Thus, both nodes will have been collecting backgroundcrosstalk signal in roughly equal amounts during the integration andwill continue to do so during the readout phase. The two nodes are readout and subtracted thereby subtracting the crosstalk signal. Note thatcharge or voltage is never explicitly transferred from the photosite tothe second storage node. The second transfer gate (for the chargetransfer architecture) or the second access switch (for the bufferedphotosite architecture) is maintained in the pixel to maximize thesymmetry of the two nodes within the pixel.

In another embodiment of the invention with large storage capacitors, inthe sensor described above as a second embodiment, the first storagenode (220) includes a first voltage sample holding capacitor (222) andan input voltage switch (224) coupled between the input buffer and thefirst voltage sample holding capacitor. The second storage node (240)includes a second voltage sample holding capacitor (242) and an inputvoltage switch (244) coupled between the input buffer and the secondvoltage sample holding capacitor. The first and second voltage sampleholding capacitors (222, 242) are disposed symmetrically about the photodetector (212). The voltage switches are as previously described. Thevoltage sample holding capacitor is a capacitance, as described below,that holds a signal value encoded as a voltage, and the capacitoroperates over a sufficient voltage range to store the range of expectedsignal values.

In another embodiment of the invention, the invention relates to adual-storage node pixel that reduces the time delay between exposures to10 μs, freezing the background lighting. The sensor provides adifference image in a single frame readout. This particular pixelemploys an in-pixel buffer to improve sensitivity which is preferablebut not required.

In the general embodiment, illustrated in FIG. 7, a pixel includes ninenFET transistors (M1-M9), one photosensitive capacitor (Cp), and twostorage node capacitors (Cn) and is driven by nine electrical controlsignals (VPR, PR, VDD, VLD, VSS, S1, S2, VD, SEL) and provides twooutput signals (OUT1, OUT2).

The photosensitive capacitor Cp is any structure which can collectoptically generated carriers. It may be an n+photodiode, an n−photodiode, a photogate or a pinned-photodiode structure. Typically, itis the largest structure in the pixel to maximize the effective quantumefficiency. Control signals VPR and PR control the reset of Cp betweenexposures and provide antiblooming within an exposure. Control signalsVDD (drain voltage), VLD (load voltage), VSS (source voltage) controlthe in-pixel buffer. Control signals S1 and S2 control the sampling ofthe buffer output onto the two storage nodes. The storage nodes Cn holdthe sampled signal for the duration of the frame readout. The controlsignals VD and SEL control the column amplifiers. Typically, the columnamplifiers are source-follower configurations where VD is connected tothe upper supply bias. A differential amplifier configuration is alsopossible by connecting VD at transistors M6 and M7 to a current source.The two column output busses OUT1 and OUT2 transmit the pixel outputsignals to the remaining analog chain outside the pixel array.

In operation, an image capture cycle includes the following timeintervals:

-   -   t_(RESET1) control signals initiate the reset of all nodes in        the pixel;    -   t_(INT1) a PR low transition initiates the first integration        period;    -   t_(s1) a S1 low transition completes sample and hold operation        of buffered output by first storage node;    -   t_(RESET2) reset the pixel and second storage node prior to        second integration;    -   t_(INT2) a PR low transition initiates the second integration        period;    -   t_(S2) an S2 low transition completes sample and hold operation        of buffered output by second storage node; and    -   t_(READ) a SEL high transition places the pixel outputs on OUT1        and OUT2

In general, the pixel will be implemented with a reduced set of controlbusses. This simplifies control and improves a quantum efficiency. Thechoice of reduced control bussing is dictated by the CMOS processproperties (number of metal layers, pinned-photodiode, thresholdvoltages, transistor characteristics), power requirements, or interfacerequirements to remaining CMOS circuitry.

The following is not meant to be inclusive but shows some of the basicalternative configurations and embodiments.

In FIG. 8, a pixel with eight control busses and with storage node bootstrapping is depicted. In this implementation, RDEN is clocked lowduring pixel reset and integration and then clocked high during readout.

In FIG. 9, a pixel with eight control busses is also depicted. However,in this implementation there is no bootstrap of the storage nodes;however, the pixel could be bootstrapped if VDD is clocked. VLD or VSmay be clocked to enable the buffer only during the integration periods.

In FIG. 10, a pixel with seven control busses is depicted. Thisimplementation uses the VDD control signal in several places and employsa substrate connection in the buffer to eliminate one control bus.

In FIG. 11, a pixel with a pFET used for pixel reset is depicted.Replacing M1 with a pFET allows the pixel to be reset to the maximumvoltage (able to accumulate a maximum number of photo electrons, of anegative charge).

A single storage node pixel is a trivial extension. This would eliminatethree transistors, one control bus (S2) and one output bus (OUT2). Amulti-storage node (n>2) pixel is also a trivial extension. Threetransistors, one control bus and one output bus would be added for eachextra storage node.

This invention relates to a CMOS image sensor with a specialized pixelto allow two images to be captured substantially contemporaneously andsubsequently read out. FIG. 12 shows the present configuration of aprototype image sensor. The image sensor of FIG. 12 only generates thedifference image as the intended application is background subtraction.Without loss of generality, it is possible to modify the analog chain todeliver both images to the output.

FIG. 12 is a block diagram of a CMOS image sensor employing a dualstorage node pixel. Other aspects of the design include the analog chainand background subtraction. The entire analog chain (pixel, columnamplifiers, pipeline, DPGA, ADC) is fully differential. Known CMOSsensors employ single-ended analog chains. The sensor is applicable forbackground subtraction of rapidly changing scenes. This inventionapplies to any CMOS sensor with in-pixel storage used for the purpose ofbackground subtraction of fast moving scenes or even for the specificapplication of background subtraction for smart air-bag deployment.

A dual storage node architecture for a CCD sensor is described in U.S.Pat. No. 5,585,652 to S. Kamasz, et al., “Method and apparatus forreal-time background illumination subtraction”, incorporated herein byreference. This patent reference utilizes some unique properties ofCCDs. In contrast, the present invention utilizes either CMOS sensorarchitecture or on chip differential amplifiers.

A photo detector node of a pinned photo diode is preferred for bestsensitivity. A single supply bus for pixel reset bias (VPR), buffer bias(VDD) and column amplifier (RDEN, read enable) is preferred for animproved fill factor. The buffer can be either continuously activated(more power dissipation) or enabled by clocking the load FET gate(greater capacitance than clocking the source).

This invention is particularly useful for background subtraction ofrapidly changing scenes. The difference in time between the signal imageand the background image is in the order of 10 microseconds. In knowntechniques, it is necessary to read out an entire image (the signalimage) before the next image (background image) can be collected. Thisprocess requires a millisecond or more in known sensors (even with highframe rates). The signal node pixels of known sensors have a greaterdelay between images (approximately 50×) compared to the short delaybetween images achievable by the present invention.

It will be appreciated by persons of ordinary skill in the this art inlight of these teachings that control circuitry as used herein includeslogic elements, memory elements, level shifter elements and driversneeded to implement the various timing and control functions needed tomake a sensor work. Such elements may be made of CMOS (complimentaryMOS), PMOS (P channel MOS), or NMOS (N channel MOS) circuits, but mayalso include bipolar technology particularly as used in bimos circuits.Bimos circuits are to be understood to include a combined MOS transistorand bipolar transistor to provide enhanced drive capability. Suchcontrol circuitry may be micro programmed controlled by memory elements(e.g., a read only memory) or by ASIC circuits (application specificintegrated circuits) or discrete timing and control circuits.

Having described preferred embodiments of a novel dual storage nodepixel for a CMOS sensor (which are intended to be illustrative and notlimiting), it is noted that modifications and variations can be made bypersons skilled in the art in light of the above teachings. It istherefore to be understood that changes may be made in the particularembodiments of the invention disclosed which are within the scope andspirit of the invention as defined by the appended claims.

1. A sensor comprising: a pixel having a photo site, a first storagenode and a second storage node; and control circuitry to transfer afirst collected signal produced by light from a first image from thephoto site to the first storage node during a first period, to transfera second collected signal produced by light from a second image from thephoto site to the second storage node during a second period thatfollows the first period, and to transfer the first and second collectedsignals out of the pixel during a third period that follows the secondperiod, wherein the first storage node includes a first capacitor and afirst reset gate coupled directly between the first capacitor and areset voltage, and wherein the second storage node includes a secondcapacitor and a second reset gate coupled directly between the secondcapacitor and the reset voltage.
 2. The sensor of claim 1, wherein: thephoto site includes a photo detector; the photo detector is one of aphotodiode and a pinned photodiode; and the first and second collectedsignals are charge type signals.
 3. A sensor comprising: a pixel thatincludes a first storage node, a second storage node and a photodetector that is one of a photodiode and a pinned photodiode; andcontrol circuitry to transfer a first collected signal produced by lightfrom a first image from the photo detector to the first storage nodeduring a first period, to transfer a second collected signal produced bylight from a second image from the photo detector to the second storagenode during a second period, and to transfer the first and secondcollected signals out of the pixel during a third period that followsthe second period, wherein the first storage node includes a firstcharge holding capacitor and a first charge transfer gate, wherein thefirst charge transfer gate is the only charge transfer gate coupledbetween the first charge holding capacitor and the photo detector,wherein the second storage node includes a second charge holdingcapacitor and a second charge transfer gate, and wherein the secondcharge transfer gate is the only charge transfer gate coupled betweenthe second charge holding capacitor and the photo detector.
 4. Thesensor of claim 3, wherein: the pixel further includes an output buffer;the first storage node further includes an output voltage switch coupledbetween the first charge holding capacitor and the output buffer; andthe second storage node further includes an output voltage switchcoupled between the second charge holding capacitor and the outputbuffer.
 5. A sensor comprising: a pixel that includes a first storagenode, a second storage node and a photo detector that is one of aphotodiode and a pinned photodiode; and control circuitry to transfer afirst collected signal produced by light from a first image from thephoto detector to the first storage node during a first period, totransfer a second collected signal produced by light from a second imagefrom the photo detector to the second storage node during a secondperiod, and to transfer the first and second collected signals out ofthe pixel during a third period that follows the second period, whereinthe first storage node includes a first charge holding capacitor, afirst output voltage switch and a first output buffer coupled betweenthe first charge holding capacitor and the first output voltage switch,and wherein the second storage node includes a second charge holdingcapacitor, a second output voltage switch and a second output buffercoupled between the second charge holding capacitor and the secondoutput voltage switch.
 6. The sensor of claim 2, wherein the photodetector is a pinned photodiode.
 7. The sensor of claim 3, wherein: thecontrol circuitry is coupled to the first charge transfer gate toprovide a first control signal that can enable charges to freelytransfer between the photo detector and the first charge holdingcapacitor throughout the first period; and the control circuitry iscoupled to the second charge transfer gate to provide a second controlsignal that can enable charges to freely transfer between the photodetector and the second charge holding capacitor throughout the secondperiod.
 8. A sensor comprising: a pixel that includes a first storagenode, a second storage node, a photo detector and a preset gate, thepreset gate being the only gate coupled between the photo detector and apreset voltage, the photo detector being one of a photodiode and apinned photodiode; and control circuitry to transfer a first collectedsignal produced by light from a first image from the photo detector tothe first storage node during a first period, to transfer a secondcollected signal produced by light from a second image from the photodetector to the second storage node during a second period, and totransfer the first and second collected signals out of the pixel duringa third period that follows the second period, wherein the controlcircuitry is coupled to the preset gate to provide the preset gate witha preset signal.
 9. The sensor of claim 8, wherein: the controlcircuitry is coupled to the preset gate to provide a preset gate controlsignal to the preset gate; and the control circuitry controls apotential of the preset signal to be less than a potential of the presetgate control signal minus a transistor threshold voltage.
 10. The sensorof claim 9, wherein the potential of the preset gate control signaldiffers from the potential of the preset signal by the transistorthreshold voltage.
 11. The sensor of claim 8, wherein: the controlcircuitry is coupled to the preset gate to provide the preset gate witha preset signal at a potential that operates as a drain; and the controlcircuitry is coupled to the preset gate to provide a preset gate controlsignal at a potential that enables the preset gate to transfer aquantity of charge into the preset signal when accumulated charges inthe photo detector exceed a capacity of the photo detector to holdcharge.
 12. The sensor of claim 8, wherein: the control circuitry iscoupled to the preset gate to provide the preset gate with the presetsignal at a potential that operates as a drain; the control circuitry iscoupled to the preset gate to provide a preset gate control signal; thecontrol circuitry provides the preset gate control signal during a firstportion of the first period at a first potential that enables the presetgate to transfer substantially all photo generated charge into thepreset signal; and the control circuitry provides the preset gatecontrol signal during a second portion of the first period at a secondpotential that enables the preset gate to transfer a quantity of chargeinto the preset signal when accumulated charges in the photo detectorexceed a capacity of the photo detector to hold charge.
 13. The sensorof claim 3, wherein: the first storage node includes a first reset gatecoupled to the first charge holding capacitor; and the second storagenode includes a second reset gate coupled to the second charge holdingcapacitor.
 14. The sensor of claim 5, further comprising: a first resetgate coupled to an input of the first output buffer; and a second resetgate coupled to an input of the second output buffer.
 15. The sensor ofclaim 3, further comprising: a first output buffer coupled to the firstcharge holding capacitor; a first row switch coupled between the firstoutput buffer and a first column bus; a second output buffer coupled tothe second charge holding capacitor; and a second row switch coupledbetween the second output buffer and a second column bus.
 16. The sensorof claim 3, wherein: the first and second charge transfer gates areformed of NMOS technology; the first storage node includes a reset gatecoupled to the first charge holding capacitor; the second storage nodeincludes a reset gate coupled to the second charge holding capacitor;and the reset gates of the first and second storage nodes are formed ofPMOS technology.
 17. The sensor of claim 4, wherein: the pixel furtherincludes a reset gate coupled to an input of the output buffer; thereset gate is formed of PMOS technology; and the first and second chargetransfer gates are formed of NMOS technology.
 18. The sensor of claim 8,wherein: the first storage node includes a first charge holdingcapacitor and a first charge transfer gate coupled between the firstcharge holding capacitor and the photo detector; the second storage nodeincludes a second charge holding capacitor and a second charge transfergate coupled between the second charge holding capacitor and the photodetector; the first and second charge transfer gates are formed of NMOStechnology; and the preset gate is formed of PMOS technology.
 19. Thesensor of claim 3, wherein: the first and second charge transfer gatesare formed of PMOS technology; the first storage node includes a resetgate coupled to the first charge holding capacitor; the second storagenode includes a reset gate coupled to the second charge holdingcapacitor; and the reset gates of the first and second storage nodes areformed of NMOS technology.
 20. The sensor of claim 4, wherein: the pixelfurther includes a reset gate coupled to an input of the output buffer;the reset gate is formed of NMOS technology; and the first and secondcharge transfer gates are formed of PMOS technology.
 21. The sensor ofclaim 8, wherein: the first storage node includes a first charge holdingcapacitor and a first charge transfer gate coupled between the firstcharge holding capacitor and the photo detector; the second storage nodeincludes a second charge holding capacitor and a second charge transfergate coupled between the second charge holding capacitor and the photodetector; the first and second charge transfer gates are formed of PMOStechnology; and the preset gate is formed of NMOS technology.
 22. Amethod of operating a pixel having a photo detector, a buffer coupled tothe photo detector, first and second storage capacitors coupled throughrespective switches to the buffer, the method comprising: resetting thephoto detector and the first and second capacitors; collecting photocharge produced by light from a first image in the photo detector;transferring the collected photo charge from the photo detector to thefirst capacitor; resetting the photo detector and the second capacitor;collecting photo charge produced by light from a second image in thephoto detector; and transferring the collected photo charge to thesecond capacitor.
 23. The method of claim 22, further comprising:illuminating a scene during the step of collecting photo charge but notilluminating the scene during the step of repeating the step ofcollecting photo charge; and transferring voltages on the first andsecond capacitors through a differential analog chain to an on chipanalog to digital converter.
 24. A method comprising: transferring afirst collected signal produced by light from a first image from a photosite to a first storage node during a first period; transferring asecond collected signal produced by light from a second image from thephoto site to a second storage node during a second period that followsthe first period; and transferring the first and second collectedsignals out of the pixel during a third period that follows the secondperiod.
 25. A sensor comprising: a pixel that includes a first storagenode, a second storage node and a photo detector; and control circuitryto transfer a first collected signal produced by light from a firstimage from the photo detector to the first storage node during a firstperiod, to transfer a second collected signal produced by light from asecond image from the photo detector to the second storage node during asecond period, and to transfer the first and second collected signals inparallel out of the pixel during a third period that follows the secondperiod.
 26. A sensor according to claim 25, wherein: the first storagenode includes a first charge holding capacitor and a first chargetransfer gate coupled between the first charge holding capacitor and thephoto detector; and the second storage node includes a second chargeholding capacitor and a second charge transfer gate coupled between thesecond charge holding capacitor and the photo detector.
 27. A sensoraccording to claim 25, wherein: the first storage node includes a firstcharge holding capacitor, a first output voltage switch and a firstoutput buffer coupled between the first charge holding capacitor and thefirst output voltage switch; and the second storage node includes asecond charge holding capacitor, a second output voltage switch and asecond output buffer coupled between the second charge holding capacitorand the second output voltage switch.
 28. A sensor according to claim25, wherein: the pixel further includes a preset gate coupled to thephoto detector; and the control circuitry is coupled to the preset gateto provide the preset gate with a preset signal.
 29. A sensor accordingto claim 25, wherein the pixel is one pixel of a two-dimensional arrayof like pixels.